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10 Reset Configuration

Every system configuration may require a different reset configuration. This can also be quite confusing. Please see the various board files for example.

10.1 jtag_nsrst_delay <ms>


How long (in milliseconds) OpenOCD should wait after deasserting nSRST before starting new JTAG operations.

10.2 jtag_ntrst_delay <ms>


Same jtag_nsrst_delay, but for nTRST

The jtag_n[st]rst_delay options are useful if reset circuitry (like a big resistor/capacitor, reset supervisor, or on-chip features). This keeps the signal asserted for some time after the external reset got deasserted.

10.3 reset_config

Note: To maintainer types and integrators. Where exactly the “reset configuration” goes is a good question. It touches several things at once. In the end, if you have a board file - the board file should define it and assume 100% that the DONGLE supports anything. However, that does not mean the target should not also make not of something the silicon vendor has done inside the chip. Grr.... nothing is every pretty.


Problems:

  1. Every JTAG Dongle is slightly different, some dongles impliment reset differently.
  2. Every board is also slightly different; some boards tie TRST and SRST together.
  3. Every chip is slightly different; some chips internally tie the two signals together.
  4. Some may not impliment all of the signals the same way.
  5. Some signals might be push-pull, others open-drain/collector.
Best Case: OpenOCD can hold the SRST (push-button-reset), then reset the TAP via TRST and send commands through the JTAG tap to halt the CPU at the reset vector before the 1st instruction is executed, and finally release the SRST signal.
Depending upon your board vendor, your chip vendor, etc, these signals may have slightly different names.

OpenOCD defines these signals in these terms:

The Command: