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Note: As of 28/nov/2008 OpenOCD does not know how to program a SPI flash that a micro may boot from. Perhaps you the reader would like to contribute support for this.
Flash Steps:
flash banks
List configured flash banks
NOTE: the singular form: 'flash bank' is used to configure the flash banks.
flash info <num>
Print info about flash bank <num>
flash probe <num>
Identify the flash, or validate the parameters of the configured flash. Operation
depends on the flash type.
flash erase_check <num>
Check erase state of sectors in flash bank <num>. This is the only operation that
updates the erase state information displayed by flash info. That means you have
to issue an erase_check command after erasing or programming the device to get
updated information.
flash protect_check <num>
Check protection state of sectors in flash bank <num>.
flash erase_sector using the same syntax.
flash erase_sector <num> <first> <last>
Erase sectors at bank <num>, starting at sector <first> up to and including
<last>. Sector numbering starts at 0. Depending on the flash type, erasing may
require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
the CFI driver).
flash erase_address <address> <length>
Erase sectors starting at <address> for <length> bytes
flash write_bank <num> <file> <offset>
Write the binary <file> to flash bank <num>, starting at
<offset> bytes from the beginning of the bank.
flash write_image [erase] <file> [offset] [type]
Write the image <file> to the current target's flash bank(s). A relocation
[offset] can be specified and the file [type] can be specified
explicitly as bin (binary), ihex (Intel hex), elf
(ELF file) or s19 (Motorola s19). Flash memory will be erased prior to programming
if the erase parameter is given.
flash protect <num> <first> <last> <on|off>
Enable (on) or disable (off) protection of flash sectors <first> to
<last> of flash bank <num>.
The flash bank command is used to configure one or more flash chips (or banks in OpenOCD terms)
flash bank <driver> <base> <size> <chip_width>
<bus_width> <target#> [driver_options ...]
Configures a flash bank at <base> of <size> bytes and <chip_width>
and <bus_width> bytes using the selected flash <driver>.
CFI flash are external flash chips - often they are connected to a specific chip select on the micro. By default at hard reset most micros have the ablity to “boot” from some flash chip - typically attached to the chips CS0 pin.
For other chip selects: OpenOCD does not know how to configure, or access a specific chip select. Instead you the human might need to via other commands (like: mww) configure additional chip selects, or perhaps configure a GPIO pin that controls the “write protect” pin on the FLASH chip.
flash bank cfi <base> <size> <chip_width> <bus_width>
<target#> [jedec_probe|x16_as_x8]
CFI flashes require the number of the target they're connected to as an additional
argument. The CFI driver makes use of a working area (specified for the target)
to significantly speed up operation.
chip_width and bus_width are specified in bytes.
The jedec_probe option is used to detect certain non-CFI flash roms, like AM29LV010 and similar types.
x16_as_x8 ???
flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
<clock> [calc_checksum]
LPC flashes don't require the chip and bus width to be specified. Additional
parameters are the <variant>, which may be lpc2000_v1 (older LPC21xx and LPC22xx)
or lpc2000_v2 (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
of the target this flash belongs to (first is 0), the frequency at which the core
is currently running (in kHz - must be an integral number), and the optional keyword
calc_checksum, telling the driver to calculate a valid checksum for the exception
vector table.
flash bank at91sam7 0 0 0 0 <target#>
AT91SAM7 flashes only require the target#, all other values are looked up after
reading the chip-id and type.
flash bank str7x <base> <size> 0 0 <target#> <variant>
variant can be either STR71x, STR73x or STR75x.
flash bank str9x <base> <size> 0 0 <target#>
The str9 needs the flash controller to be configured prior to Flash programming, eg.
str9x flash_config 0 4 2 0 0x80000
This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
flash bank str9xpec <base> <size> 0 0 <target#>
Before using the flash commands the turbo mode will need enabling using str9xpec
enable_turbo <num>.
Only use this driver for locking/unlocking the device or configuring the option bytes. Use the standard str9 driver for programming. See STR9 specific commands.
flash bank stellaris <base> <size> 0 0 <target#>
stellaris flash plugin only require the target#.
flash bank stm32x <base> <size> 0 0 <target#>
stm32x flash plugin only require the target#.
flash bank aduc702x <base> <size> 0 0 <target#>
aduc702x flash plugin require the flash base, size and target#.
mflash bank <soc> <base> <chip_width> <bus_width>
<RST pin> <WP pin> <DPD pin> <target #>
Configures a mflash for <soc> host bank at
<base>. <chip_width> and <bus_width> are bytes
order. Pin number format is dependent on host GPIO calling convention.
If WP or DPD pin was not used, write -1. Currently, mflash bank
support s3c2440 and pxa270.
(ex. of s3c2440) mflash <RST pin> is GPIO B1, <WP pin> and <DPD pin> are not used.
mflash bank s3c2440 0x10000000 2 2 1b -1 -1 0
(ex. of pxa270) mflash <RST pin> is GPIO 43, <DPD pin> is not used and <DPD pin> is GPIO 51.
mflash bank pxa270 0x08000000 2 2 43 -1 51 0
The flash configuration is deduced from the chip identification register. The flash controller handles erases automatically on a page (128/265 byte) basis so erase is not necessary for flash programming. AT91SAM7 processors with less than 512K flash only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes that can be erased separatly. Only an EraseAll command is supported by the controller for each flash plane and this is called with
These are flash specific commands when using the str9xpec driver.
Note: Before using the str9xpec driver here is some background info to help you better understand how the drivers works. OpenOCD has two flash drivers for the str9.
Before we run any cmds using the str9xpec driver we must first disable the str9 core. This example assumes the str9xpec driver has been configured for flash bank 0.
# assert srst, we do not want core running
# while accessing str9xpec flash driver
jtag_reset 0 1
# turn off target polling
poll off
# disable str9 core
str9xpec enable_turbo 0
# read option bytes
str9xpec options_read 0
# re-enable str9 core
str9xpec disable_turbo 0
poll on
reset halt
The above example will read the str9 option bytes. When performing a unlock remember that you will not be able to halt the str9 - it has been locked. Halting the core is not required for the str9xpec driver as mentioned above, just issue the cmds above manually or from a telnet prompt.
eg. str9x flash_config 0 4 2 0 0x80000
This will setup
BBSR - Boot Bank Size register
NBBSR - Non Boot Bank Size register
BBADR - Boot Bank Start Address register
NBBADR - Boot Bank Start Address register
These are flash specific commands when using the stm32x driver.
These are flash specific commands when using the Stellaris driver.