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JTAG Pinout

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Amontec JTAGkey related links

Amontec JTAGkey
Undedicated USB to JTAG cable
Based on FTDI FT2232
Amontec JTAG Pinout
Including Official ARM 20-pin Connector ( JTAG Pin-out )
Amontec JTAG Accelerator
Now fully supported by OpenOCD JTAG software.
Amontec sdk4arm
Software Dev. Kit for ARM
Eclipse - GCC - OpenOCD - JTAGkey - your arm target board


Amontec Chameleon Links

Amontec Chameleon POD The generic JTAG interface Dongle
Amontec ARM Debug ValuePack
The easiest way for ARM JTAG and other ARM debug
Amontec JTAG Accelerator
The solution to flash ARM via JTAG at 363Kbytes/sec.
Amontec Chameleon Programmer Configure your POD in the minute with pre-compiled configurations.

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The Generic USB to JTAG interface cable :
Amontec JTAGkey jtagkey_small02

 > Home > Online > Dev. Zone > JTAG Pinout

All Common JTAG Pinout

Official ARM 20-pin Header / JTAG connector pin-out

      VTref   1 2  Vsupply
     nTRST  3 4  GND
     TDI    5 6  GND
     TMS    7 8  GND
     TCK    9 10 GND
     RTCK   11 12 GND
     TDO    13 14 GND
     nSRST  15 16 GND
     DBGRQ  17 18 GND
     DBGACK 19 20 GND

Guide Lines for building your Target Board JTAG interface

  1. All ground pins must be connected.
  2. DBGRQ and DBGACK are rarely used; they connect to lines on the ARM core that are rarely brought out to physical pins and are manipulated via other means (as bits in the jtag chain?).
  3. nSRST is the system reset (active low) and it is optional but recommended as Multi-ICE and RealView ICE uses is for debug of XScale processors, reset on startup, reset from the debugger, and reset detection and is needed for Auto Configuration on some processors.
  4. nTRST is optional, it resets the JTAG TAP controller state mahine and the embedded ICE logic. Resetting of the TAP controller can be accomplished by 5 TCK cycles with TMS high> AT91SAM7 CPUs don't bring nTRST to a pin. OpenOCD can be configured to work with or without nTRST and nSRST. Both reset signals are open drain.
  5. RTCK is an optional readback on the TCK pin and is used for adaptive clocking.
  6. Vsupply is used to power the JTAG dongle and
  7. VTref is used to set the thresholds. ARM's official jtag interfaces put a 10K pulldown resistor on these lines.
  8. ARM recommends 10K pullups/pulldowns with pullups on TMS, TDI, TDO, nSRST, and nTRST and a pulldown (odd) on TCK. Atmel's AT91SAM7 eval board uses pullup on TCK. Multi-ICE, RealView ICE, and OpenOCD support other devices on the JTAG chain, however manual configuration may be required. Multi-ICE uses analog switches (between ground and VTref) to drive the JTAG signals with 100 ohm series resistors.

Minimized ARM 20-pin Header / JTAG connector pin-out

Amontec “JTAGkey 20-pin Header” ( see www.amontec.com/jtagkey.shtml )

      VREF    1 2  n.c
     TRST_N 3 4  GND
     TDI    5 6  GND
     TMS    7 8  GND
     TCK    9 10 GND
     n.c.   11 12 GND
     TDO    13 14 GND
     SRST_N 15 16 GND
     n.c.   17 18 GND
     n.c.   19 20 GND

n.c. for not connected

Xilinx JTAG - Altera JTAG - Lattice JTAG pinout

AVR JTAG - MIPS JTAG- XSCALE JTAG - ALL JTAG pinout

see this document

amt_ann003_small68wide

pdfmid   [952k]

 

 

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